A Histogram-Based Digital Background Calibration Technique for Pipelined A/D Converters

This paper presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs) to correct the gain error due to the capacitors mismatch and finite dc gain and nonlinearity error owing to the residue amplifiers. The proposed calibration scheme corrects these errors by using the histogram-based method. To calculate the linear and nonlinear coefficients, the threshold level of sub-ADC is changed and based on specifications of residue characteristic and output histogram, the first and third order coefficients are extracted. This method does not require any calibration signal or additional analog hardware and relaxes the performance requirements of the analog building circuits. Circuit level simulation results of a 12-bit 100 MS/s pipelined ADC in a 65 nm CMOS technology show that the proposed calibration scheme improves signal-to-noise and distortion (SNDR) and spurious free dynamic range (SFDR) from 30.4 dB and 31.8 dB to 69.3 dB and 81.2 dB, respectively.