基于动态电压调度的温度自适应低负载电路合成

Swaroop Ghosh, S. Bhunia, K. Roy
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引用次数: 2

摘要

由于封装的冷却能力有限,功率密度的增加会导致芯片过热。传统的热管理技术,如逻辑关闭、时钟门控、频率缩放、同步电压频率调谐等,增加了设计复杂性和/或显著降低了性能。本文提出了一种新的设计方法,利用动态电压调度(DVS)使电路适应温度自适应。它是通过一种合成技术来完成的,(a)隔离和预测可能在变化下变得关键的路径集,(b)确保它们很少被激活,(c)通过自适应时钟拉伸在这些路径中容忍可能的延迟故障(在降低电压下)。这使我们能够在温度升高时安排较低的电源电压,而不需要频率调谐。在一个示例管道上的仿真结果表明,该设计与传统设计的温度降低效果相似,性能损失仅为11%,面积开销仅为14%。相反,由于工作频率降低,传统的管道设计会导致50%的性能下降
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling
Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, frequency scaling, simultaneous voltage-frequency tuning etc. increase the design complexity and/or degrade the performance significantly. In this paper, the authors propose a novel design technique, which makes a circuit amenable to temperature adaptation using dynamic voltage scheduling (DVS). It is accomplished by a synthesis technique that (a) isolates and predicts the set of paths that may become critical under variations, (b) ensures they are activated rarely, and (c) tolerates possible delay failures (at reduced voltage) in these paths by adaptive clock stretching. This allows us to schedule a lower supply voltage during increased temperature without requiring frequency tuning. Simulation results on an example pipeline show that proposed design yields similar temperature reduction as conventional design with only 11% performance penalty and 14% area overhead. The conventional pipeline design, on contrary, leads to 50% performance degradation due to reduced operating frequency
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