{"title":"用于电化学传感器的6.5 μ w 70-dB 0.18 μm CMOS恒电位Delta-Sigma","authors":"Joan Aymerich, M. Dei, L. Terés, F. Serra-Graells","doi":"10.1109/PRIME.2018.8430329","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a low-power potentiostatic second-order continuous-time (CT) delta-sigma modulator $( \\Delta \\Sigma \\mathrm {M})$ for the amperometric read-out and A/D conversion of electrochemical sensors. The proposed architecture reuses the sensor itself as a leaky integrator stage for shaping the quantization noise, resulting in a very compact and energy efficient read-out front end. Low-power CMOS circuits are also presented for the remaining analog blocks of the $\\Delta \\Sigma \\mathrm {M}$ loop. A design example in $0 . 18-{\\mu }\\mathrm {m}$ CMOS technology is provided with a total area of $0 . 063$mm2. Post-layout simulations show a dynamic range of 70dB with an overall power consumption of $6 . 5{\\mu }\\mathrm {W}$ at $1 . 8-\\mathrm {V}$ supply.","PeriodicalId":384458,"journal":{"name":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"53 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 6.5-μW 70-dB 0.18-μm CMOS Potentiostatic Delta-Sigma for Electrochemical Sensors\",\"authors\":\"Joan Aymerich, M. Dei, L. Terés, F. Serra-Graells\",\"doi\":\"10.1109/PRIME.2018.8430329\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a low-power potentiostatic second-order continuous-time (CT) delta-sigma modulator $( \\\\Delta \\\\Sigma \\\\mathrm {M})$ for the amperometric read-out and A/D conversion of electrochemical sensors. The proposed architecture reuses the sensor itself as a leaky integrator stage for shaping the quantization noise, resulting in a very compact and energy efficient read-out front end. Low-power CMOS circuits are also presented for the remaining analog blocks of the $\\\\Delta \\\\Sigma \\\\mathrm {M}$ loop. A design example in $0 . 18-{\\\\mu }\\\\mathrm {m}$ CMOS technology is provided with a total area of $0 . 063$mm2. Post-layout simulations show a dynamic range of 70dB with an overall power consumption of $6 . 5{\\\\mu }\\\\mathrm {W}$ at $1 . 8-\\\\mathrm {V}$ supply.\",\"PeriodicalId\":384458,\"journal\":{\"name\":\"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)\",\"volume\":\"53 6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PRIME.2018.8430329\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRIME.2018.8430329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 6.5-μW 70-dB 0.18-μm CMOS Potentiostatic Delta-Sigma for Electrochemical Sensors
This paper presents the design of a low-power potentiostatic second-order continuous-time (CT) delta-sigma modulator $( \Delta \Sigma \mathrm {M})$ for the amperometric read-out and A/D conversion of electrochemical sensors. The proposed architecture reuses the sensor itself as a leaky integrator stage for shaping the quantization noise, resulting in a very compact and energy efficient read-out front end. Low-power CMOS circuits are also presented for the remaining analog blocks of the $\Delta \Sigma \mathrm {M}$ loop. A design example in $0 . 18-{\mu }\mathrm {m}$ CMOS technology is provided with a total area of $0 . 063$mm2. Post-layout simulations show a dynamic range of 70dB with an overall power consumption of $6 . 5{\mu }\mathrm {W}$ at $1 . 8-\mathrm {V}$ supply.