Hossein Mohammadnezhad, Alireza Karimi Bidhendi, Michael M. Green, P. Heydari
{"title":"低功耗BiCMOS 50 Gbps gm增强双反馈跨阻放大器","authors":"Hossein Mohammadnezhad, Alireza Karimi Bidhendi, Michael M. Green, P. Heydari","doi":"10.1109/BCTM.2015.7340578","DOIUrl":null,"url":null,"abstract":"A single-channel 50 Gbps transimpedance amplifier (TIA) in 130nm SiGe BiCMOS process is presented. The proposed TIA is comprised of a gm-boosted dual-feedback common-base, an RC-degenerated common-emitter and an inductively degenerated emitter-follower. Accounting for 100 fF photodiode's input capacitance, the TIA achieves a measured transimpedance gain of 41 dBÍÍ and a measured RMS input-referred current-noise spectral density of 35.4 pA/√Hz over a wide 3dB-bandwidth greater than 50 GHz. It achieves an open eye at 50 Gbps with an RMS jitter of 2.3 ps (including the jitter contribution of test fixture). The TIA chip occupies 1×0.575 mm2 (including pads) of die area and dissipates 24 mW from a 2 V supply voltage (i.e., less than 0.5 mW per 1 Gbps).","PeriodicalId":126143,"journal":{"name":"2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A low-power BiCMOS 50 Gbps Gm-boosted dual-feedback transimpedance amplifier\",\"authors\":\"Hossein Mohammadnezhad, Alireza Karimi Bidhendi, Michael M. Green, P. Heydari\",\"doi\":\"10.1109/BCTM.2015.7340578\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-channel 50 Gbps transimpedance amplifier (TIA) in 130nm SiGe BiCMOS process is presented. The proposed TIA is comprised of a gm-boosted dual-feedback common-base, an RC-degenerated common-emitter and an inductively degenerated emitter-follower. Accounting for 100 fF photodiode's input capacitance, the TIA achieves a measured transimpedance gain of 41 dBÍÍ and a measured RMS input-referred current-noise spectral density of 35.4 pA/√Hz over a wide 3dB-bandwidth greater than 50 GHz. It achieves an open eye at 50 Gbps with an RMS jitter of 2.3 ps (including the jitter contribution of test fixture). The TIA chip occupies 1×0.575 mm2 (including pads) of die area and dissipates 24 mW from a 2 V supply voltage (i.e., less than 0.5 mW per 1 Gbps).\",\"PeriodicalId\":126143,\"journal\":{\"name\":\"2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCTM.2015.7340578\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2015.7340578","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-power BiCMOS 50 Gbps Gm-boosted dual-feedback transimpedance amplifier
A single-channel 50 Gbps transimpedance amplifier (TIA) in 130nm SiGe BiCMOS process is presented. The proposed TIA is comprised of a gm-boosted dual-feedback common-base, an RC-degenerated common-emitter and an inductively degenerated emitter-follower. Accounting for 100 fF photodiode's input capacitance, the TIA achieves a measured transimpedance gain of 41 dBÍÍ and a measured RMS input-referred current-noise spectral density of 35.4 pA/√Hz over a wide 3dB-bandwidth greater than 50 GHz. It achieves an open eye at 50 Gbps with an RMS jitter of 2.3 ps (including the jitter contribution of test fixture). The TIA chip occupies 1×0.575 mm2 (including pads) of die area and dissipates 24 mW from a 2 V supply voltage (i.e., less than 0.5 mW per 1 Gbps).