面向100gs /s及以上的CMOS adc

2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2016-10-01 DOI:10.1109/CSICS.2016.7751033

L. Kull, D. Luu, P. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, A. Cevrero, I. Oezkaya, Hazar Yueksel, T. Toifl

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引用次数: 8

摘要

分析了在32nm CMOS SOI上实现64倍时间交错ADC的方法。测量结果证实，在90 GS/s和1.2V电源下，33 dB SNDR高达19.9 GHz。架构细节和分析显示了所选架构的局限性和潜力。对于大于64 GS/s的adc来说，输入带宽尤其值得关注，因为较大数量的采样开关会增加寄生负载并降低输入带宽。重点介绍了对交织器结构的简化分析和现有带宽问题解决方案的见解，并展示了将CMOS adc的采样速度扩展到100 GS/s以上的途径。

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CMOS ADCs Towards 100 GS/s and Beyond

The implementation of a 64x time-interleaved ADC in 32nm CMOS SOI is analyzed. Measurement results confirm 33 dB SNDR up to 19.9 GHz at 90 GS/s and 1.2V supply. Architecture details and analysis show insights into limitations and potentials of the chosen architecture. In par-ticular the input bandwidth is of concern for ADCs at more than 64 GS/s, as a larger number of sampling switches in-creases the parasitic load and reduces the input bandwidth. Insights on a simplified analysis of interleaver structures and existing solutions to bandwidth issues are highlighted and show a path to extend the sampling speed of CMOS ADCs beyond 100 GS/s.

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2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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