{"title":"基于40纳米CMOS的100 mvpp输入范围10 khz BW vco的CT-DSM神经记录IC","authors":"W. Zhou, W. Goh, Yi Chen, Tantan Zhang, Yuan Gao","doi":"10.1109/SOCC46988.2019.1570553458","DOIUrl":null,"url":null,"abstract":"This paper presents a time-domain continuous-time sigma delta modulator (CT-DSM) based neuro-recording interface circuit. This circuit consists of a current-reuse fully differential OTA, a voltage-controlled oscillator (VCO), a counter-based quantizer and a capacitive DAC feedback circuit with Data Weighted Averaging (DWA) logic. A current-reuse Gm cell is adopted to suppress the input-referred noise with high energy efficiency. The VCO converts the input signal amplitude into phase for integration as well as quantization by the counter-based quantizer. The DAC feedback circuit ensures a linear operation of Gm-VCO within the input range. The prototype circuit is designed and implemented in a commercial 40-nm CMOS process. the proposed circuit consumes 19.5 $\\mu$ W under 1.2-V supply voltage. With the maximum tolerable input swing of 100-mVpp, the proposed circuit achieves an SNDR of 59 dB over a bandwidth of 10 kHz. The proposed design is suitable for application such as the neuro-recording circuit in the closed-loop neural stimulation system.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 100-mVpp Input Range 10-kHz BW VCO-based CT-DSM Neuro-Recording IC in 40-nm CMOS\",\"authors\":\"W. Zhou, W. Goh, Yi Chen, Tantan Zhang, Yuan Gao\",\"doi\":\"10.1109/SOCC46988.2019.1570553458\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a time-domain continuous-time sigma delta modulator (CT-DSM) based neuro-recording interface circuit. This circuit consists of a current-reuse fully differential OTA, a voltage-controlled oscillator (VCO), a counter-based quantizer and a capacitive DAC feedback circuit with Data Weighted Averaging (DWA) logic. A current-reuse Gm cell is adopted to suppress the input-referred noise with high energy efficiency. The VCO converts the input signal amplitude into phase for integration as well as quantization by the counter-based quantizer. The DAC feedback circuit ensures a linear operation of Gm-VCO within the input range. The prototype circuit is designed and implemented in a commercial 40-nm CMOS process. the proposed circuit consumes 19.5 $\\\\mu$ W under 1.2-V supply voltage. With the maximum tolerable input swing of 100-mVpp, the proposed circuit achieves an SNDR of 59 dB over a bandwidth of 10 kHz. The proposed design is suitable for application such as the neuro-recording circuit in the closed-loop neural stimulation system.\",\"PeriodicalId\":253998,\"journal\":{\"name\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC46988.2019.1570553458\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC46988.2019.1570553458","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 100-mVpp Input Range 10-kHz BW VCO-based CT-DSM Neuro-Recording IC in 40-nm CMOS
This paper presents a time-domain continuous-time sigma delta modulator (CT-DSM) based neuro-recording interface circuit. This circuit consists of a current-reuse fully differential OTA, a voltage-controlled oscillator (VCO), a counter-based quantizer and a capacitive DAC feedback circuit with Data Weighted Averaging (DWA) logic. A current-reuse Gm cell is adopted to suppress the input-referred noise with high energy efficiency. The VCO converts the input signal amplitude into phase for integration as well as quantization by the counter-based quantizer. The DAC feedback circuit ensures a linear operation of Gm-VCO within the input range. The prototype circuit is designed and implemented in a commercial 40-nm CMOS process. the proposed circuit consumes 19.5 $\mu$ W under 1.2-V supply voltage. With the maximum tolerable input swing of 100-mVpp, the proposed circuit achieves an SNDR of 59 dB over a bandwidth of 10 kHz. The proposed design is suitable for application such as the neuro-recording circuit in the closed-loop neural stimulation system.