基于40纳米CMOS的100 mvpp输入范围10 khz BW vco的CT-DSM神经记录IC

W. Zhou, W. Goh, Yi Chen, Tantan Zhang, Yuan Gao
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引用次数: 1

摘要

提出了一种基于时域连续σ δ调制器(CT-DSM)的神经记录接口电路。该电路由一个电流复用的全差分OTA、一个压控振荡器(VCO)、一个基于计数器的量化器和一个带有数据加权平均(DWA)逻辑的电容式DAC反馈电路组成。采用电流复用Gm电池抑制输入参考噪声,具有较高的能量效率。VCO将输入信号的幅度转换为相位,通过基于计数器的量化器进行积分和量化。DAC反馈电路确保Gm-VCO在输入范围内的线性运行。该原型电路采用商用40纳米CMOS工艺设计和实现。在1.2 v供电电压下,电路功耗为19.5 $\mu$ W。在最大可容忍输入摆幅为100 mvpp的情况下,该电路在10 kHz带宽上实现了59 dB的SNDR。该设计适用于闭环神经刺激系统中的神经记录电路等应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 100-mVpp Input Range 10-kHz BW VCO-based CT-DSM Neuro-Recording IC in 40-nm CMOS
This paper presents a time-domain continuous-time sigma delta modulator (CT-DSM) based neuro-recording interface circuit. This circuit consists of a current-reuse fully differential OTA, a voltage-controlled oscillator (VCO), a counter-based quantizer and a capacitive DAC feedback circuit with Data Weighted Averaging (DWA) logic. A current-reuse Gm cell is adopted to suppress the input-referred noise with high energy efficiency. The VCO converts the input signal amplitude into phase for integration as well as quantization by the counter-based quantizer. The DAC feedback circuit ensures a linear operation of Gm-VCO within the input range. The prototype circuit is designed and implemented in a commercial 40-nm CMOS process. the proposed circuit consumes 19.5 $\mu$ W under 1.2-V supply voltage. With the maximum tolerable input swing of 100-mVpp, the proposed circuit achieves an SNDR of 59 dB over a bandwidth of 10 kHz. The proposed design is suitable for application such as the neuro-recording circuit in the closed-loop neural stimulation system.
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