三层抗蚀剂压印技术及其在MOSFET制造中的应用

Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387) Pub Date : 2000-07-11 DOI:10.1109/IMNC.2000.872730

H. Nakamura, A. Baba, T. Asano

{"title":"三层抗蚀剂压印技术及其在MOSFET制造中的应用","authors":"H. Nakamura, A. Baba, T. Asano","doi":"10.1109/IMNC.2000.872730","DOIUrl":null,"url":null,"abstract":"In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.","PeriodicalId":270640,"journal":{"name":"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Imprint lithography using triple-layer-resist and its application to MOSFET fabrication\",\"authors\":\"H. Nakamura, A. Baba, T. Asano\",\"doi\":\"10.1109/IMNC.2000.872730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.\",\"PeriodicalId\":270640,\"journal\":{\"name\":\"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMNC.2000.872730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMNC.2000.872730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文报道了采用三层抗蚀剂的压印方法的图案转移特性。此外，还演示了栅极长度低至100nm的mosfet的制造。为了研究压印应力对器件的机械损伤，还测试了栅极氧化物的完整性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Imprint lithography using triple-layer-resist and its application to MOSFET fabrication

In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Papers Microprocesses and Nanotechnology 2000. 2000 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.00EX387)

自引率

0.00%

发文量