Matrix-vector Multiplication on a Fixed Size Unidirectional Systolic Array

In this paper, the problem of multiplication of matrix A=(aik)nxn by vector b macr= (bk)nxl unidirectional linear systolic array (ULSA) comprised of ples[n/2] processing elements is considered. To match the dimension of matrix A to the ULSA size, the partitioning of the matrix A into quasidiagonal blocks is performed. Each block contains p quasidiagonals. In order to decrease the computation time the reordering of elements of block matrices and resulting vector c is performed. The global structure of memory interface subsystem (MIS) is proposed. The MIS, located between the host and ULSA, provides corresponding data transfers to/from ULSA. Finally, the performance of synthesized ULSA is discussed and compared with fixed size bidirectional systolic array.