一种强大的CMOS逻辑技术,用于构建具有高效流水线的高频电路

E. Gayles, K. Acken, R. Owens, M. J. Irwin
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引用次数: 0

摘要

当前的细粒度流水线技术,如True单相,允许高频电路设计,但代价是每次操作的显著延迟。另一方面,低延迟设计需要复杂的流水线级电路,这在设计高时钟频率系统时是不可行的。在本文中,我们提出了一种新的CMOS电路技术,允许高频电路和每次操作的低周期延迟。我们的技术不同于其他逻辑家族,这些逻辑家族试图通过在过程变化和信号耦合的情况下更加健壮来提供相同的优势。为了证明我们的电路技术的可行性,我们还提出了一个使用该电路技术的64位进位前瞻加法器,它能够每2.0纳秒计算一个64位加法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A robust CMOS logic technique for building high frequency circuits with efficient pipelining
Current fine grain pipelining techniques, such as True Single-Phase, allow for high frequency circuit design at the cost of significant latency per operation. On the other hand, low latency designs require complex circuitry within pipeline stages, which is not feasible when designing high clock frequency systems. In this paper, we propose a novel CMOS circuit technique that allows both high frequency circuits and low cycle latency per operation. Our technique differs from other logic families that have attempted to provide the same advantages by being more robust in the presence of process variations and signal coupling. To show the feasibility of our circuit technique, we also present a 64 bit carry-lookahead adder using this circuit technique that is capable of calculating a 64 bit add every 2.0 nanoseconds.
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