Perimeter effects in small geometry bipolar transistors

The fundamental limits on device performance imposed by geometrical effects are studied. Results of an extensive three-dimensional (3D) device simulation study are given and compared with experimental results of a 0.25- mu m bipolar technology. It is shown in this study that geometrical factors alone can result in lower DC current gain and lower f/sub T/ at low current densities for smaller devices. It is also shown that perimeter effects are beneficial for small emitter devices at high current densities. This is a particularly important design consideration for high current operation as in BiCMOS gates.<>