Power and Delay optimization of Master Slave SR Flip Flop using QFGMOS for Low Power Applications

In the present era, as the technology becomes more advanced so the demand for low power and lesser delay devices has increased. So keeping that in mind this paper has presented the design of NAND based Master Slave SRFF using Quasi Floating Gate MOS (QFGMOS) and it has been verified through the simulation that the proposed circuit consumes less power and delay than that of CMOS based SRFF. The performance of the proposed work has been verified through LtSpice simulation tool using 130nm PTM technology with the supply voltage of 1V.