{"title":"超标量处理器并发故障检测方法","authors":"A. Pawlovsky, M. Hanawa","doi":"10.1109/ATS.1992.224418","DOIUrl":null,"url":null,"abstract":"The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instruction's slots that sometimes fill some of the pipelines (stages) in an ILP processor. The authors show the practical application of this method to a superscalar RISC processor. For this processor, branch addresses, execution of certain instructions (store/load) and resource conflicts that force the inclusion of NOPs are the cases exploited to test its pipelines. The NOPs are replaced by an effective instruction running in another pipeline. This allows the checking of the processor's pipelines by the comparison of the outputs of their stages during the execution of the replicated instruction.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A concurrent fault detection method for superscalar processors\",\"authors\":\"A. Pawlovsky, M. Hanawa\",\"doi\":\"10.1109/ATS.1992.224418\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instruction's slots that sometimes fill some of the pipelines (stages) in an ILP processor. The authors show the practical application of this method to a superscalar RISC processor. For this processor, branch addresses, execution of certain instructions (store/load) and resource conflicts that force the inclusion of NOPs are the cases exploited to test its pipelines. The NOPs are replaced by an effective instruction running in another pipeline. This allows the checking of the processor's pipelines by the comparison of the outputs of their stages during the execution of the replicated instruction.<<ETX>>\",\"PeriodicalId\":208029,\"journal\":{\"name\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1992.224418\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224418","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A concurrent fault detection method for superscalar processors
The authors describe a method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method makes use of the No Operation (NOP) instruction's slots that sometimes fill some of the pipelines (stages) in an ILP processor. The authors show the practical application of this method to a superscalar RISC processor. For this processor, branch addresses, execution of certain instructions (store/load) and resource conflicts that force the inclusion of NOPs are the cases exploited to test its pipelines. The NOPs are replaced by an effective instruction running in another pipeline. This allows the checking of the processor's pipelines by the comparison of the outputs of their stages during the execution of the replicated instruction.<>
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