{"title":"ULSI多层铜互连的电化学沉积技术","authors":"C. Ting, D. Papapanayiotou, Mei Zhu","doi":"10.1109/ICSICT.1998.785852","DOIUrl":null,"url":null,"abstract":"Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Electro-chemical deposition technology for ULSI multilevel copper interconnects\",\"authors\":\"C. Ting, D. Papapanayiotou, Mei Zhu\",\"doi\":\"10.1109/ICSICT.1998.785852\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.\",\"PeriodicalId\":286980,\"journal\":{\"name\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1998.785852\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.785852","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electro-chemical deposition technology for ULSI multilevel copper interconnects
Copper is a promising candidate to replace aluminum for better conductivity, reliability as well as lower cost. A new electrochemical copper deposition (ECD) process has been developed for the manufacturing of ULSI damascened, or in-laid, Cu interconnects. The new Cu ECD process-is designed for filling trenches and vias with high aspect ratio (AR) conductor structures for 0.25 um device generation and beyond. The gap filling Cu deposition process is capable of high deposition rate and gives good material properties as well as good uniformity. The newly developed Cu ECD system has a standard cluster tool configuration. Its deposition modules have in-situ rinse/dry capability to achieve cassette to cassette dry wafer in and dry wafer out operations. Dual damascene structures with 0.4 um feature size and AR 5:1, which represents the most aggressive device structure being made today, have been completely filled without voids or seams. In addition, deep contact test structures with 0.25 um feature size and AR 8:1 have also been filled to demonstrate the capabilities of this new technology.