{"title":"一种新型电流模平方电路,可补偿载流子迁移率降低引起的误差","authors":"M. Al-Absi, Ibrahim A. As-Sabban","doi":"10.1109/ELECO.2013.6713861","DOIUrl":null,"url":null,"abstract":"This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation techniques to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18μm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.16 % and the power consumption is 331μW.","PeriodicalId":108357,"journal":{"name":"2013 8th International Conference on Electrical and Electronics Engineering (ELECO)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A new current-mode squaring circuit with compensation for error resulting from carrier mobility reduction\",\"authors\":\"M. Al-Absi, Ibrahim A. As-Sabban\",\"doi\":\"10.1109/ELECO.2013.6713861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation techniques to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18μm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.16 % and the power consumption is 331μW.\",\"PeriodicalId\":108357,\"journal\":{\"name\":\"2013 8th International Conference on Electrical and Electronics Engineering (ELECO)\",\"volume\":\"145 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 8th International Conference on Electrical and Electronics Engineering (ELECO)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELECO.2013.6713861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 8th International Conference on Electrical and Electronics Engineering (ELECO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECO.2013.6713861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new current-mode squaring circuit with compensation for error resulting from carrier mobility reduction
This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation techniques to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18μm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.16 % and the power consumption is 331μW.