{"title":"35nm栅极In0.7Ga0.3As/In0.52Al0.48As HEMT","authors":"I. Watanabe, A. Endoh, T. Mimura, T. Matsui","doi":"10.1109/ICIPRM.2007.380681","DOIUrl":null,"url":null,"abstract":"We fabricated a 35-nm-gate In0.7Ga0.3As/In0.52Al0.48As high electron mobility transistor by using a simple, self-aligned one-step-recessed gate procedure. An extrinsic maximum transconductance (gm_max) of 1.7 S/mm and a current gain cutoff frequency (fT) of 520 GHz were achieved at room temperature. This significantly high fT was obtained by reducing the gate length to 35 nm and using an epitaxial structure with a 3-nm-thick InAlAs spacer layer, a 6-nm-thick InAlAs Schottky barrier layer and a 2-nm-thick InP etching stopper layer to decrease the gate-to-channel distance to 8 nm, and form simultaneously 50-nm-long side-recess structures and T-shaped gates stacked on the InAlAs Schottky barrier layer. These results are the first experimental achievement of fT as high as 520 GHz by using the one-step-recessed gate procedure.","PeriodicalId":352388,"journal":{"name":"2007 IEEE 19th International Conference on Indium Phosphide & Related Materials","volume":"297 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"35-nm-Gate In0.7Ga0.3As/In0.52Al0.48As HEMT with 520-GHz fT\",\"authors\":\"I. Watanabe, A. Endoh, T. Mimura, T. Matsui\",\"doi\":\"10.1109/ICIPRM.2007.380681\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We fabricated a 35-nm-gate In0.7Ga0.3As/In0.52Al0.48As high electron mobility transistor by using a simple, self-aligned one-step-recessed gate procedure. An extrinsic maximum transconductance (gm_max) of 1.7 S/mm and a current gain cutoff frequency (fT) of 520 GHz were achieved at room temperature. This significantly high fT was obtained by reducing the gate length to 35 nm and using an epitaxial structure with a 3-nm-thick InAlAs spacer layer, a 6-nm-thick InAlAs Schottky barrier layer and a 2-nm-thick InP etching stopper layer to decrease the gate-to-channel distance to 8 nm, and form simultaneously 50-nm-long side-recess structures and T-shaped gates stacked on the InAlAs Schottky barrier layer. These results are the first experimental achievement of fT as high as 520 GHz by using the one-step-recessed gate procedure.\",\"PeriodicalId\":352388,\"journal\":{\"name\":\"2007 IEEE 19th International Conference on Indium Phosphide & Related Materials\",\"volume\":\"297 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-05-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE 19th International Conference on Indium Phosphide & Related Materials\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIPRM.2007.380681\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE 19th International Conference on Indium Phosphide & Related Materials","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIPRM.2007.380681","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
35-nm-Gate In0.7Ga0.3As/In0.52Al0.48As HEMT with 520-GHz fT
We fabricated a 35-nm-gate In0.7Ga0.3As/In0.52Al0.48As high electron mobility transistor by using a simple, self-aligned one-step-recessed gate procedure. An extrinsic maximum transconductance (gm_max) of 1.7 S/mm and a current gain cutoff frequency (fT) of 520 GHz were achieved at room temperature. This significantly high fT was obtained by reducing the gate length to 35 nm and using an epitaxial structure with a 3-nm-thick InAlAs spacer layer, a 6-nm-thick InAlAs Schottky barrier layer and a 2-nm-thick InP etching stopper layer to decrease the gate-to-channel distance to 8 nm, and form simultaneously 50-nm-long side-recess structures and T-shaped gates stacked on the InAlAs Schottky barrier layer. These results are the first experimental achievement of fT as high as 520 GHz by using the one-step-recessed gate procedure.