提高嵌入式栅极垂直晶体管的可靠性和减小寄生电容效应

2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI:10.1109/IPFA.2009.5232696

Jyi-Tsong Lin, C. Kuo, Tai-Yi Lee, Y. Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, Chih-Hung Sun, Hsien-Nan Chiu

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引用次数: 3

摘要

本文提出了一种新型的嵌入式栅极垂直侧壁MOSFET (EGVMOS)，以减少传统VMOS的寄生电容。仿真结果表明，在VDs = 0.05 V和1.0 V时，EGVMOS不仅可以实现86.34%和54.76%的Cgd降低，而且由于抑制了扭结效应，与传统的VMOS相比，器件的可靠性得到了提高。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate

We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional VMOS.

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2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

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