具有灵活10Kb存储器的CMOS 12K门阵列

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156670

M. Takechi, K. Ikuzaki, T. Itoh, M. Fujita, M. Asano, A. Masaki, T. Matsunaga

{"title":"具有灵活10Kb存储器的CMOS 12K门阵列","authors":"M. Takechi, K. Ikuzaki, T. Itoh, M. Fujita, M. Asano, A. Masaki, T. Matsunaga","doi":"10.1109/ISSCC.1984.1156670","DOIUrl":null,"url":null,"abstract":"A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A CMOS 12K gate array with flexible 10Kb memory\",\"authors\":\"M. Takechi, K. Ikuzaki, T. Itoh, M. Fujita, M. Asano, A. Masaki, T. Matsunaga\",\"doi\":\"10.1109/ISSCC.1984.1156670\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156670\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156670","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

本文将介绍一种2μm CMOS栅极，该栅极在整个布线区域内具有晶体管，适用于实现12,000逻辑门和10,000位存储器。还将介绍具有16-word×8bits RAM(访问时间为16ns)和16-word×10b先入/先出内存的单个阵列。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A CMOS 12K gate array with flexible 10Kb memory

A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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