器件结构和栅极堆叠工艺对硅纳米线晶体管低频噪声的影响

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI:10.1109/asicon47005.2019.8983679

E. Simoen, A. Oliveira, A. Veloso, A. Chasin, R. Ritzenthaler, H. Mertens, N. Horiguchi, C. Claeys

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引用次数: 3

摘要

结构和栅极堆栈处理对水平纳米线(NW)晶体管的低频噪声性能有明显影响。在这项工作中，比较了单纳米线与堆叠器件的噪声。对于单个NWs，无结(JL)晶体管往往比反转模式(IM)晶体管表现出更好的噪声性能。此外，还将演示金属栅极(MG)类型对1/f噪声功率谱密度(PSD)的明显影响。

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Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors

As will be shown, the architecture and gate stack processing have a clear impact on the low-frequency noise performance of horizontal nanowire (NW) transistors. In this work, the noise of single nanowires is compared with stacked devices. For single NWs, junctionless (JL) transistors tend to exhibit a better noise performance than inversion mode (IM) counterparts. In addition, a clear impact of the type of metal gate (MG) on the 1/f noise Power Spectral Density (PSD) will be demonstrated.

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2019 IEEE 13th International Conference on ASIC (ASICON)

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