A programmable I/O buffer supported multiple differential standard based on 28nm technology

This paper introduces a programmable I/O buffer that supports multiple differential standards. It is integrated in a 28nm process FPGA to implement the communication between the FPGA core and external circuits. Under different standards, its data transmission rate can reach 1.25Gbps. In the article, the design idea of important circuit modules that work with I/O buffer, such as single-ended to differential-ended module, and bias signal generation module are also introduced. On the other hand, because all circuit designs use 1.8V devices and the supply voltage of the supported differential standard is higher than 1.8V, it also has a voltage withstand function under 2.5V power supply. After the circuit design is completed, the layout is drawn. According to the simulation results, its function is correct and the transmission rate can reach the design value.