{"title":"用于热成像应用的硅层外延铅硫族化物","authors":"H. Zogg","doi":"10.1117/12.368352","DOIUrl":null,"url":null,"abstract":"Narrow gap Pb1-xSnxSe and PbTe layers grown epitaxially on Si(111)-substrates by molecular beam epitaxy (MBE) exhibit high quality despite the large lattice and thermal expansion mismatch. A buffer layer of CaF2 is employed for compatibility. Due to easy glide of misfit dislocations in the lead chalcogenide layers, thermal strains relax even at cryogenic temperatures and after many temperature cycling. This is partly due to the NaCl- structure of lead salts and at variance to the zinkblende- type semiconductors. In addition, the high permittivity of lead chalcodenides which effectively shields the electric fields from charged defects makes the materials rather forgiving, i.e. higher quality devices are obtained from lower quality material, again at variance to Hg1-xCdxTe or GaAs related compounds. Photovoltaic p-n or Schottky-barrier sensor arrays are delineated by using standard photolithography. At low temperatures, the ultimate sensitivities are presently limited by defects, mainly dislocations. At higher temperatures, the ultimate theoretical sensitivity have been obtained in Schottky barrier devices, this despite the large mismatch and only 3 micrometers thickness of the layers. Due to the rather low temperatures used during the MBE and delineation, sensor arrays are obtained by postprocessing even on active Si- substrates. We describe ways to further improve device performance by lowering the dislocation densities in the lattice mismatched layers. This is achieved by temperature rampings, which drive out the threading dislocations from the active parts of the sensors. Presently, densities of 1 X 106 cm-2 in layers of a few micrometer thickness are obtained. These densities are sufficiently low in order not to dominate the leakage currents in real devices even at 80K temperatures.","PeriodicalId":276773,"journal":{"name":"Material Science and Material Properties for Infrared Optics","volume":"163 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Epitaxial lead-chalcogenide on silicon layers for thermal imaging applications\",\"authors\":\"H. Zogg\",\"doi\":\"10.1117/12.368352\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Narrow gap Pb1-xSnxSe and PbTe layers grown epitaxially on Si(111)-substrates by molecular beam epitaxy (MBE) exhibit high quality despite the large lattice and thermal expansion mismatch. A buffer layer of CaF2 is employed for compatibility. Due to easy glide of misfit dislocations in the lead chalcogenide layers, thermal strains relax even at cryogenic temperatures and after many temperature cycling. This is partly due to the NaCl- structure of lead salts and at variance to the zinkblende- type semiconductors. In addition, the high permittivity of lead chalcodenides which effectively shields the electric fields from charged defects makes the materials rather forgiving, i.e. higher quality devices are obtained from lower quality material, again at variance to Hg1-xCdxTe or GaAs related compounds. Photovoltaic p-n or Schottky-barrier sensor arrays are delineated by using standard photolithography. At low temperatures, the ultimate sensitivities are presently limited by defects, mainly dislocations. At higher temperatures, the ultimate theoretical sensitivity have been obtained in Schottky barrier devices, this despite the large mismatch and only 3 micrometers thickness of the layers. Due to the rather low temperatures used during the MBE and delineation, sensor arrays are obtained by postprocessing even on active Si- substrates. We describe ways to further improve device performance by lowering the dislocation densities in the lattice mismatched layers. This is achieved by temperature rampings, which drive out the threading dislocations from the active parts of the sensors. Presently, densities of 1 X 106 cm-2 in layers of a few micrometer thickness are obtained. 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引用次数: 5
摘要
通过分子束外延(MBE)在Si(111)衬底上外延生长窄间隙Pb1-xSnxSe和PbTe层,尽管存在较大的晶格和热膨胀失配,但仍具有较高的质量。CaF2的缓冲层用于兼容性。由于失配位错在硫族铅层中容易滑动,即使在低温下和经过多次温度循环后,热应变也会松弛。这部分是由于铅盐的NaCl结构和锌闪锌矿型半导体的差异。此外,铅的高介电常数有效地屏蔽了电场对带电缺陷的影响,使得材料相当宽容,即从较低质量的材料中获得高质量的器件,再次与Hg1-xCdxTe或GaAs相关化合物不同。光伏p-n或肖特基势垒传感器阵列通过使用标准光刻技术来描绘。在低温下,极限灵敏度目前受到缺陷(主要是位错)的限制。在更高的温度下,在肖特基势垒器件中获得了最终的理论灵敏度,尽管存在很大的失配并且层的厚度只有3微米。由于在MBE和描绘过程中使用了相当低的温度,因此即使在有源Si衬底上也可以通过后处理获得传感器阵列。我们描述了通过降低晶格错配层中的位错密度来进一步提高器件性能的方法。这是通过温度陡坡来实现的,温度陡坡可以从传感器的有源部分驱除螺纹错位。目前,在几微米厚度的层中获得了1 X 106 cm-2的密度。这些密度足够低,即使在80K温度下也不会主导实际设备中的泄漏电流。
Epitaxial lead-chalcogenide on silicon layers for thermal imaging applications
Narrow gap Pb1-xSnxSe and PbTe layers grown epitaxially on Si(111)-substrates by molecular beam epitaxy (MBE) exhibit high quality despite the large lattice and thermal expansion mismatch. A buffer layer of CaF2 is employed for compatibility. Due to easy glide of misfit dislocations in the lead chalcogenide layers, thermal strains relax even at cryogenic temperatures and after many temperature cycling. This is partly due to the NaCl- structure of lead salts and at variance to the zinkblende- type semiconductors. In addition, the high permittivity of lead chalcodenides which effectively shields the electric fields from charged defects makes the materials rather forgiving, i.e. higher quality devices are obtained from lower quality material, again at variance to Hg1-xCdxTe or GaAs related compounds. Photovoltaic p-n or Schottky-barrier sensor arrays are delineated by using standard photolithography. At low temperatures, the ultimate sensitivities are presently limited by defects, mainly dislocations. At higher temperatures, the ultimate theoretical sensitivity have been obtained in Schottky barrier devices, this despite the large mismatch and only 3 micrometers thickness of the layers. Due to the rather low temperatures used during the MBE and delineation, sensor arrays are obtained by postprocessing even on active Si- substrates. We describe ways to further improve device performance by lowering the dislocation densities in the lattice mismatched layers. This is achieved by temperature rampings, which drive out the threading dislocations from the active parts of the sensors. Presently, densities of 1 X 106 cm-2 in layers of a few micrometer thickness are obtained. These densities are sufficiently low in order not to dominate the leakage currents in real devices even at 80K temperatures.