界面电荷(Qit)和界面阱密度(Dit)对A12O3、ZrO2和HfO2基纳米多栅极器件的影响

R. Thakur, Pragati Singh
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引用次数: 1

摘要

随着该技术的迅速缩小,隔离氧化物半导体层以防止载流子隧穿到栅极变得越来越困难,因此泄漏正在成为纳米领域应用的基于MOSFET的半导体器件的主要威胁。本文提出了一种用High-k代替原来的sio2来实现硅- sio2之间良好隔离的方法。在本研究中,发现氧化铪(HfO2)和氧化锆(ZrO2)是sih的良好替代品。利用Sentaurus TCAD对该装置进行了仿真,并用MATLAB进行了数学计算。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effects of Interface Charge (Qit) and Interface Trap Density (Dit) on A12O3, ZrO2 and HfO2 based Nano Regime Multi-Gate Devices
As the technology has been scaling down very rapidly, it is becoming diflicult to isolate the oxide-semiconductor layer to prevent tunneling of carriers to the gate and thus the leakage is becoming a major threat in MOSFET based semiconductor devices for applications in the Nano Regime. In this paper, a method for having a good isolation between Si-SiO2has been shown by replacing the earlier SiO2With High-k. In this study, Hafnium Oxide (HfO2) and Zirconium Oxide (ZrO2) were found to be the good alternatives for Sifh.The device was simulated using Sentaurus TCAD and mathematical calculations were done using MATLAB.
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