单片3.3 V CCD/SOI-CMOS成像技术

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) Pub Date : 2000-12-10 DOI:10.1109/IEDM.2000.904414

V. Suntharalingam, B. Burke, M. Cooper, D. Yost, P. Gouker, M. Anthony, H. Whittingham, J. Sage, J. Burns, S. Rabe, C. Chen, J. Knecht, S. Cann, P. Wyatt, C. Keast

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引用次数: 10

摘要

我们开发了一种合并CCD/SOI-CMOS技术，可以在芯片上制造单片低功耗成像系统。在块柄晶圆中制造的CCD的电荷转移效率约为1/spl倍/10/sup -5/，并且在3.3 v时钟和8/spl倍/8-/spl μ /m像素下具有超过100,000个电子的良好容量。完全耗尽的0.35-/spl mu/m SOI-CMOS环形振荡器在3.3 V时级延迟为48 ps。我们首次展示了具有电荷域A/D转换和片上时钟的集成图像传感器。

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Monolithic 3.3 V CCD/SOI-CMOS imager technology

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1/spl times/10/sup -5/ and well capacities of more than 100,000 electrons with 3.3-V clocks and 8/spl times/8-/spl mu/m pixels. Fully depleted 0.35-/spl mu/m SOI-CMOS ring oscillators have stage delay of 48 ps at 3.3 V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.

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International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)

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