Easily testable and fault-tolerant design of FFT butterfly networks

In this paper, we first propose a testable design scheme for FFT butterfly networks based on M-testability conditions. Based on them, a novel design-for-testability approach is presented and applied to the module-level systolic FFT arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, a reconfiguration mechanism is used to bypass the faulty cell and the testable/fault-tolerant FFT networks are constructed. Special cell designs are presented which implement the reconfiguration mechanism. The reliability of the FFT system increases significantly. The chip design for the bit-level butterfly module is presented. The hardware overhead is low - about 12% for the bit-level design. For the module-level design, it leads to a lower hardware overhead (about 1/2N, where N is the computation point).