S. Oniga, A. Tisan, D. Mic, A. Buchman, A. Vida-Ratiu
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Optimizing FPGA implementation of Feed-Forward Neural Networks
This paper presents an in depth study of FPGA implementation of feed-forward neural networks regarding error reduction as a function of number of bits used for weights representation. Xilinx block parameters influence on resources occupied by network and the maximum working frequency is also studied.