L. Li, Mingyuan Xu, Xingfa Huang, X. Shen, D. Fu, Xi Chen, Pujie
{"title":"一个12位500MS/S无sha ADC在0.18um CMOS","authors":"L. Li, Mingyuan Xu, Xingfa Huang, X. Shen, D. Fu, Xi Chen, Pujie","doi":"10.1109/INEC.2016.7589282","DOIUrl":null,"url":null,"abstract":"In this paper, a 12 bit 500MS/s SHA-less ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier(MDAC). A 0.18pm CMOS process with 3.3V/1.8V analog power supply is used in the design. This ADC achieves an SNR of 65dB and an SFDR of 82dB for sampling analog input frequencies up to 250MHz.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 12 Bit 500MS/S SHA-less ADC in 0.18um CMOS\",\"authors\":\"L. Li, Mingyuan Xu, Xingfa Huang, X. Shen, D. Fu, Xi Chen, Pujie\",\"doi\":\"10.1109/INEC.2016.7589282\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 12 bit 500MS/s SHA-less ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier(MDAC). A 0.18pm CMOS process with 3.3V/1.8V analog power supply is used in the design. This ADC achieves an SNR of 65dB and an SFDR of 82dB for sampling analog input frequencies up to 250MHz.\",\"PeriodicalId\":416565,\"journal\":{\"name\":\"2016 IEEE International Nanoelectronics Conference (INEC)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Nanoelectronics Conference (INEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INEC.2016.7589282\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Nanoelectronics Conference (INEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INEC.2016.7589282","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, a 12 bit 500MS/s SHA-less ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier(MDAC). A 0.18pm CMOS process with 3.3V/1.8V analog power supply is used in the design. This ADC achieves an SNR of 65dB and an SFDR of 82dB for sampling analog input frequencies up to 250MHz.
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