低成本部分扫描设计:一个高层次的综合方法

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) Pub Date : 1998-04-26 DOI:10.1109/VTEST.1998.670887

M. Flottes, R. Pires, B. Rouzeyre, L. Volpe

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引用次数: 3

摘要

本文提出了一种局部扫描设计的高阶合成方法。高水平的可测试性信息被用来指导合成过程的设计与最少数量的扫描寄存器。这些设计可以实现最大的故障覆盖率。该方法主要依赖于对寄存器分配过程的临时修改。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low cost partial scan design: a high level synthesis approach

In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.

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Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

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