{"title":"拓扑开关随机存取存储器(TRAM)的工艺与器件技术","authors":"N. Takaura","doi":"10.1109/INEC.2014.7460331","DOIUrl":null,"url":null,"abstract":"The process and device technologies of “topological-switching RAM” (TRAM) were investigated. The sputtering and dry etching of GeTe/Sb2Te3 superlattice were developed as 300-mm-wafer processes. Fabrication and analyses of one-resistor and one-transistor one-resistor micro test structures revealed the electrical properties that were different from conventional phase change memory (PRAM).","PeriodicalId":188668,"journal":{"name":"2014 IEEE International Nanoelectronics Conference (INEC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Process and device technologies of topological-switching random-access memory (TRAM)\",\"authors\":\"N. Takaura\",\"doi\":\"10.1109/INEC.2014.7460331\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The process and device technologies of “topological-switching RAM” (TRAM) were investigated. The sputtering and dry etching of GeTe/Sb2Te3 superlattice were developed as 300-mm-wafer processes. Fabrication and analyses of one-resistor and one-transistor one-resistor micro test structures revealed the electrical properties that were different from conventional phase change memory (PRAM).\",\"PeriodicalId\":188668,\"journal\":{\"name\":\"2014 IEEE International Nanoelectronics Conference (INEC)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Nanoelectronics Conference (INEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INEC.2014.7460331\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Nanoelectronics Conference (INEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INEC.2014.7460331","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Process and device technologies of topological-switching random-access memory (TRAM)
The process and device technologies of “topological-switching RAM” (TRAM) were investigated. The sputtering and dry etching of GeTe/Sb2Te3 superlattice were developed as 300-mm-wafer processes. Fabrication and analyses of one-resistor and one-transistor one-resistor micro test structures revealed the electrical properties that were different from conventional phase change memory (PRAM).
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