Analysis and design of CMOS Manchester adders with variable carry-skip

A popular VLSI adder implementation is the Manchester adder using dynamic (precharge) logic, where the ripple-carry propagation delay of a block is proportional to the square of its size. The authors examine two different CMOS implementations of the Manchester adder, analyzing them with the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, they develop efficient (polynomial) algorithms to determine near-optimal, as well as optimal, block sizes for the one-level Manchester adder with variable carry-skip.<>