{"title":"一种直接转换的WLAN接收机","authors":"Jingguang Wang, Jinju Wang, Yumei Huang, Weilun Shen, Xiaofeng Yi, Zhiliang Hong","doi":"10.1109/ICASIC.2005.1611341","DOIUrl":null,"url":null,"abstract":"A direct conversion receiver for WLAN 802.11b is presented in 0.18/spl mu/m CMOS technology. It contains a complete receiver chain with low noise amplifier, I/Q mixer, programmable gain amplifier and base band filter. A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q mixer. The reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f noise. The noise figure of receiver is 5.2dB, the IIP3 is -14.5dBm at high gain setting. With the supply voltage of 1.8V, the over all power consummation is about 100mW. The chip area with pads is 2.6mm/spl times/2.5mm.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"08 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A direct conversion WLAN receiver\",\"authors\":\"Jingguang Wang, Jinju Wang, Yumei Huang, Weilun Shen, Xiaofeng Yi, Zhiliang Hong\",\"doi\":\"10.1109/ICASIC.2005.1611341\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A direct conversion receiver for WLAN 802.11b is presented in 0.18/spl mu/m CMOS technology. It contains a complete receiver chain with low noise amplifier, I/Q mixer, programmable gain amplifier and base band filter. A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q mixer. The reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f noise. The noise figure of receiver is 5.2dB, the IIP3 is -14.5dBm at high gain setting. With the supply voltage of 1.8V, the over all power consummation is about 100mW. The chip area with pads is 2.6mm/spl times/2.5mm.\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"08 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611341\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611341","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A direct conversion receiver for WLAN 802.11b is presented in 0.18/spl mu/m CMOS technology. It contains a complete receiver chain with low noise amplifier, I/Q mixer, programmable gain amplifier and base band filter. A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q mixer. The reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f noise. The noise figure of receiver is 5.2dB, the IIP3 is -14.5dBm at high gain setting. With the supply voltage of 1.8V, the over all power consummation is about 100mW. The chip area with pads is 2.6mm/spl times/2.5mm.
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