A σ = 0.66 LSB 8-bit Time-to-Digital Converter with Variable Resolution in a 180nm CMOS Technology

This work presents an 8-bit Time-to-Digital Converter (TDC) suitable for time-lapse measurement applications. The proposed TDC is composed of two nested 4-bit counters, a digital-logic control network, a register, and a decoder. Verilog language was used to synthesize the TDC using the standard cells of the technology. The system has a standard digital output and it is powered by a 1.8 V supply with a total power consumption of 9.86 mW. The characterization was performed by means of post-layout simulations using a TSMC 180 nm CMOS technology. The proposed structure exhibits a 355.4 μm × 105.8 μm area. In addition, this TDC has a standard deviation of 0.66 LSB with a fixed input time interval with a user-select operation frequency from 1 MHz to 1 GHz.