sram中位/组写使能故障的BIST算法

Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004. Pub Date : 2004-08-09 DOI:10.1109/MTDT.2004.1

S. Adham, B. Nadeau-Dostie

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引用次数: 4

摘要

在内存中使用组(或位)写入使能在嵌入式内存中变得非常普遍。用于实现这些功能的电路需要使用特定的测试顺序对不同类型的缺陷进行彻底的测试。然而，大多数BIST算法都假定在BIST运行的全局写周期中，这些写启用项被强制激活。本文提出了一种串行接口BIST算法，用于检测这些存储器的位/组写使能缺陷。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A BIST algorithm for bit/group write enable faults in SRAMs

The use of group (or bit) write enable in memories is becoming very common in embedded memories. The circuitry used to achieve these functions need be thoroughly tested for different kind of defects using specific test sequence. However, most BIST algorithms assume that these write enables are forced active during the global write cycle in the BIST run. This paper presents a serial interface BIST algorithm that is used to test defect on bit/group write enables of these memories.

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Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.

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