{"title":"一种60pJ, 3时钟上升时间，VTH损耗补偿字线升压电路，用于0.5V电源嵌入式/分立dram","authors":"S. Tanakamaru, K. Takeuchi","doi":"10.1109/IMW.2009.5090572","DOIUrl":null,"url":null,"abstract":"A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-Line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs\",\"authors\":\"S. Tanakamaru, K. Takeuchi\",\"doi\":\"10.1109/IMW.2009.5090572\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.\",\"PeriodicalId\":113507,\"journal\":{\"name\":\"2009 IEEE International Memory Workshop\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Memory Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW.2009.5090572\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2009.5090572","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-Line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs
A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.
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