{"title":"RIC/DICMOS -多通道CMOS格式化器","authors":"A. Syed","doi":"10.1109/TEST.2003.1270838","DOIUrl":null,"url":null,"abstract":"NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pinelectronics channels at up to 800 Mbps. The timing accuracy for both the formatted edges, and the strobe markers, is specified at +I81ps. The drive side minimum pulse-width is 1 ns, and the receive side can strobe pin-electronics comparator outputs as narrow as 800 ps. This paper describes the major features and operation of the new CMOS formatter.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"RIC/DICMOS - multichannel CMOS formatter\",\"authors\":\"A. Syed\",\"doi\":\"10.1109/TEST.2003.1270838\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pinelectronics channels at up to 800 Mbps. The timing accuracy for both the formatted edges, and the strobe markers, is specified at +I81ps. The drive side minimum pulse-width is 1 ns, and the receive side can strobe pin-electronics comparator outputs as narrow as 800 ps. This paper describes the major features and operation of the new CMOS formatter.\",\"PeriodicalId\":236182,\"journal\":{\"name\":\"International Test Conference, 2003. Proceedings. ITC 2003.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Test Conference, 2003. Proceedings. ITC 2003.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2003.1270838\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Test Conference, 2003. Proceedings. ITC 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2003.1270838","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pinelectronics channels at up to 800 Mbps. The timing accuracy for both the formatted edges, and the strobe markers, is specified at +I81ps. The drive side minimum pulse-width is 1 ns, and the receive side can strobe pin-electronics comparator outputs as narrow as 800 ps. This paper describes the major features and operation of the new CMOS formatter.