利用原位掺杂多晶硅薄膜的结晶诱导应力制备无位错栅工艺

C. Hashimoto, H. Miura, K. Asayama, H. Ohta, S. Ikeda
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引用次数: 3

摘要

只提供摘要形式。原位掺杂多晶硅薄膜已被发现用于半微米技术,因为薄膜沉积过程简单,薄膜表面相当平坦。实验评价了薄膜的特性,并将其应用于栅极材料。结果表明,该薄膜比传统的POCl/sub - 3/处理多晶硅薄膜具有更好的耐HF渗透性能,并具有良好的表面平整度。然而,使用原位掺杂多晶硅栅极的mosfet存在异常漏电流,而使用常规POCl/sub 3/处理多晶硅栅极的mosfet漏电流低且稳定。发现异常漏电流是由栅极边缘硅衬底位错引起的。薄膜必须完全退火,以消除栅极边缘的位错,这导致mosfet的泄漏电流水平低而稳定。>
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Dislocation free gate process using in-situ doped polysilicon thin films by crystallization-induced stress of the films
Summary form only given. In situ doped polysilicon thin films have been found useful for half-micron technology because the film deposition process is simple and the film surface is rather flat. The characteristics of the film are evaluated experimentally to apply it to a gate electrode material. It is confirmed that the film has much better tolerance to HF penetration than the conventional POCl/sub 3/-treated polysilicon thin film, and has good surface flatness. However, abnormal leakage current is observed in MOSFETs using the in situ doped polysilicon gate, while the leakage current of the MOSFETs using the conventional POCl/sub 3/ treated polysilicon gate is low and stable. The abnormal leakage current is found to be caused by dislocations in the silicon substrate at the gate edges. The films must be annealed fully to eliminate dislocations at the gate edges, which results in a low and stable leakage current level of MOSFETs. >
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