{"title":"数字音频高阶锁相环型减抖动电路的优化技术","authors":"W. Wong","doi":"10.1109/ICCE.1995.518023","DOIUrl":null,"url":null,"abstract":"Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better jitter attenuation when compared with that using maximum phase margin.","PeriodicalId":306595,"journal":{"name":"Proceedings of International Conference on Consumer Electronics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1995-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Optimization techniques for high order phase-locked loop type jitter reduction circuit for digital audio\",\"authors\":\"W. Wong\",\"doi\":\"10.1109/ICCE.1995.518023\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better jitter attenuation when compared with that using maximum phase margin.\",\"PeriodicalId\":306595,\"journal\":{\"name\":\"Proceedings of International Conference on Consumer Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.1995.518023\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.1995.518023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization techniques for high order phase-locked loop type jitter reduction circuit for digital audio
Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better jitter attenuation when compared with that using maximum phase margin.