数字音频高阶锁相环型减抖动电路的优化技术

W. Wong
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引用次数: 1

摘要

本文讨论了增益降峰和VCXO频率选择等技术。与使用最大相位裕度相比,新的增益峰值降低准则提供了更好的抖动衰减。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimization techniques for high order phase-locked loop type jitter reduction circuit for digital audio
Techniques like gain peaking reduction and the selection of voltage-controlled-crystal-oscillator (VCXO) frequency are addressed in this paper. The new gain peaking reduction criterion provides far better jitter attenuation when compared with that using maximum phase margin.
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