Area-Efficient High-Voltage (HV) Lateral MOSFETs for Discrete Device Development and Power IC Integration

This paper reports the design of area-efficient high voltage lateral MOSFETs for discrete device development and also for integration in power IC development. Utilizing the three metal layered back-end-of-the-line (BEOL) process, the footprint of the devices has been significantly reduced without any deviation from the static electrical performances. The reported devices were fabricated on a six-inch N epi/P epi/ 4H-SiC N+ substrate. The reported HV lateral devices are the best in class with superior breakdown voltage (BV) - specific on-resistance (Ron,sp) trade-off. The devices demonstrated a BV of 430V at drain-source current (Ids) of 1mA and a Ron,sp,active of 6.2 mΩ⸱cm2 at a gate-source voltage (Vgs) of 25V at 25 °C.