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引用次数: 2
摘要
基于上下文的自适应二进制算术编码器(CABAC)是H.264主配置文件视频编码器中生成最终比特流的重要组成部分。随着大规模并行H.264编码器的发展和高清晰度视频需求的提高,并行编码器的视频编码路径日益成为瓶颈。本文提出了一种全流水线的硬件CABAC编码器来加速比特流的生成,该编码器适用于多核芯片中的节点处理器的加速。编码器采用类似cpu的执行风格,并使用语法元素指令(Syntax Elements Instructions, SEI)来驱动管道。采用SIMC 0.13um技术合成结果表明,本设计采用3.21K逻辑门、3.5K RAM位和34.375K ROM位,可实现590Mbps的高吞吐量,基本支持实时高清视频编码1。
A fully pipelined CABAC coder using syntax element instructions driving
Context-based Adaptive Binary Arithmetic Coder (CABAC) is an essential part in the H.264 main profile video encoder to generate final bitstream. With the development of large-scale parallel H.264 encoder and the high definition video requirement, it increasingly poses a bottleneck in the video encoding path of the parallel encoders. This paper proposes a fully pipelined hardware CABAC coder to speed up the bitstream generation, which is suitable for accelerating a node processor in a manycore chip. The coder employs a CPU-like execution style and using the Syntax Elements Instructions (SEI) to drive the pipeline. Synthesis results with SIMC 0.13um technology show that with an area of 3.21K logic gates, 3.5K RAM bits and 34.375K ROM bits, this design can achieve a high throughput of 590Mbps, basically supporting the real-time HD video coding1.