{"title":"精确几何规划-兼容摆率建模的两级运算放大器设计优化","authors":"Eric J. Wyers","doi":"10.1109/APCCAS55924.2022.10090335","DOIUrl":null,"url":null,"abstract":"Monomial models for the two-stage operational amplifier positive and negative slew rate performances are proposed in this work to aid the integrated circuit designer in producing optimal designs within the geometric programming design framework. Compared to the commonly-used and inaccurate slew rate design equations, the developed slew rate monomial models are capable of producing designs which have excellent slew rate performance agreement between the design optimization framework and circuit simulation, are based on highly-accurate slew rate design equations, require minimal overhead to produce, and have minimal modeling complexity with respect to the number of parameters to be estimated. We demonstrate the efficacy of the proposed slew rate models via a design test case in a standard 1.8-V, $0.18-\\mu \\mathbf{m}$ CMOS technology.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization\",\"authors\":\"Eric J. Wyers\",\"doi\":\"10.1109/APCCAS55924.2022.10090335\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Monomial models for the two-stage operational amplifier positive and negative slew rate performances are proposed in this work to aid the integrated circuit designer in producing optimal designs within the geometric programming design framework. Compared to the commonly-used and inaccurate slew rate design equations, the developed slew rate monomial models are capable of producing designs which have excellent slew rate performance agreement between the design optimization framework and circuit simulation, are based on highly-accurate slew rate design equations, require minimal overhead to produce, and have minimal modeling complexity with respect to the number of parameters to be estimated. We demonstrate the efficacy of the proposed slew rate models via a design test case in a standard 1.8-V, $0.18-\\\\mu \\\\mathbf{m}$ CMOS technology.\",\"PeriodicalId\":243739,\"journal\":{\"name\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS55924.2022.10090335\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090335","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization
Monomial models for the two-stage operational amplifier positive and negative slew rate performances are proposed in this work to aid the integrated circuit designer in producing optimal designs within the geometric programming design framework. Compared to the commonly-used and inaccurate slew rate design equations, the developed slew rate monomial models are capable of producing designs which have excellent slew rate performance agreement between the design optimization framework and circuit simulation, are based on highly-accurate slew rate design equations, require minimal overhead to produce, and have minimal modeling complexity with respect to the number of parameters to be estimated. We demonstrate the efficacy of the proposed slew rate models via a design test case in a standard 1.8-V, $0.18-\mu \mathbf{m}$ CMOS technology.