用于IBM令牌环局域网的16 Mbps适配器芯片

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56733

K. W. Lang, C. Erdelyi, J. L. Lamphere, S. F. Oakland, J. D. Blair, A. Correale, H. C. Cranford, D. A. Dombrowski, C. R. Hoffman, Joseph Kinman Lee, J. M. Mullen, V. R. Norman

{"title":"用于IBM令牌环局域网的16 Mbps适配器芯片","authors":"K. W. Lang, C. Erdelyi, J. L. Lamphere, S. F. Oakland, J. D. Blair, A. Correale, H. C. Cranford, D. A. Dombrowski, C. R. Hoffman, Joseph Kinman Lee, J. M. Mullen, V. R. Norman","doi":"10.1109/CICC.1989.56733","DOIUrl":null,"url":null,"abstract":"A 9.02-mm×9.02-mm chip built in 1-μm CMOS with two levels of metal and an addition mask level for fabricating capacitors is described. It contains both analog and digital circuits and has provisions for self-test. The functions include the transmitter, receiver, protocol handler, and microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. 24 K circuits of standard cell gates, 10 K circuits equivalent hand-honed custom microprocessor, and an analog macro form the physical design terrains. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 16 Mbps adapter chip for the IBM token-ring local area network\",\"authors\":\"K. W. Lang, C. Erdelyi, J. L. Lamphere, S. F. Oakland, J. D. Blair, A. Correale, H. C. Cranford, D. A. Dombrowski, C. R. Hoffman, Joseph Kinman Lee, J. M. Mullen, V. R. Norman\",\"doi\":\"10.1109/CICC.1989.56733\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 9.02-mm×9.02-mm chip built in 1-μm CMOS with two levels of metal and an addition mask level for fabricating capacitors is described. It contains both analog and digital circuits and has provisions for self-test. The functions include the transmitter, receiver, protocol handler, and microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. 24 K circuits of standard cell gates, 10 K circuits equivalent hand-honed custom microprocessor, and an analog macro form the physical design terrains. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"113 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56733\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56733","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

介绍了一种基于1 μm CMOS的9.02-mm×9.02-mm芯片，该芯片具有两层金属和一个附加掩模层，用于制造电容器。它包含模拟和数字电路，并提供自检。这些功能包括发送器、接收器、协议处理程序和微处理器，以及RAM/ROM存储、IBM PC总线、IBM PS/2总线、IBM 3174总线和Motorola 68000总线的接口。24k标准单元门电路，10k等效手工珩磨定制微处理器电路，以及模拟宏构成物理设计地形。该芯片使用单个5v电源，额定功耗为0.8 W，速度为16mb /s。该芯片还可以以4mb /s的速度运行

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A 16 Mbps adapter chip for the IBM token-ring local area network

A 9.02-mm×9.02-mm chip built in 1-μm CMOS with two levels of metal and an addition mask level for fabricating capacitors is described. It contains both analog and digital circuits and has provisions for self-test. The functions include the transmitter, receiver, protocol handler, and microprocessor, as well as interfaces for RAM/ROM storage, IBM PC bus, IBM PS/2 bus, IBM 3174 bus, and Motorola 68000 bus. 24 K circuits of standard cell gates, 10 K circuits equivalent hand-honed custom microprocessor, and an analog macro form the physical design terrains. The chip operates from a single 5-V supply, and the power consumption is 0.8 W nominal at 16 Mb/s. The chip can also be operated at 4 Mb/s

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来源期刊

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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