{"title":"6.5 MHz 34-B NCO[数控振荡器]的实现","authors":"Shi Yunhua, Sheng Shimin, L. Yue, Ji Lijiu","doi":"10.1109/ICSICT.1995.500067","DOIUrl":null,"url":null,"abstract":"An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Implementation of a 6.5 MHz 34-B NCO [numerically controlled oscillator]\",\"authors\":\"Shi Yunhua, Sheng Shimin, L. Yue, Ji Lijiu\",\"doi\":\"10.1109/ICSICT.1995.500067\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.\",\"PeriodicalId\":286176,\"journal\":{\"name\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1995.500067\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th International Conference on Solid-State and IC Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1995.500067","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
采用标准的2 /spl μ m p阱CMOS工艺，研制了一种流水线结构的数控振荡器芯片。典型的最大输入时钟速率为6.5 MHz。通过分析，改进的限速因素是累加器的延迟和ROM的数据采集速率。通过使用改进的流水线结构和n阱CMOS技术，时钟速率超过10 MHz的NCO器件确实是可能的。
Implementation of a 6.5 MHz 34-B NCO [numerically controlled oscillator]
An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.
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