基于深度神经网络架构与应用的面积高效近似MAC单元的设计与实现

Lahari P. L, S. Yellampalli, Renuka Chowdary Bheemana, R. Vaddi
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引用次数: 0

摘要

乘法累加单元是本文的主题,它被用来提高处理器的整体速度。使用乘累加单元的数字信号处理的应用包括卷积、数字滤波器、图像、视频和音频等。当考虑到图像和视频处理应用时,精度不被优先考虑,因此建立了一个近似的乘法累积单元。与Xilinx ISE 14.5中模拟的浮点乘法累积单元相比,该近似乘法累积单元以及由近似乘法器、近似加法器和近似累加器组成的浮点和近似MAC之间的各种参数(如面积、延迟和速度)进行了比较。近似乘法累加单元使用更少的空间(减少66%),延迟缩短75%,所有这些都有助于其高速度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and Implementation of Area Efficient Approximate MAC Unit for Deep Neural Network based Architectures and Applications
The Multiply Accumulate Unit, which is utilized to boost the processor's overall speed, is the subject of this essay. Applications for digital signal processing that use multiply-accumulate units include convolution, digital filters, image, video, and audio, among others. Accuracy is not given priority when image and video processing applications are taken into account, hence an approximate multiply-accumulate unit is built. This approximate multiply-accumulate unit, compared to a floating point multiply-accumulate unit simulated in Xilinx ISE 14.5, and various parameters like area, delay, and speed are compared between floating and approximate MAC consisting of an approximate multiplier efficient, an approximate adder, and an approximate accumulator. The approximate multiply-accumulate unit uses less space (66% less) and has a 75% shorter delay, all of which contribute to its high speed.
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