Implications of record peak current density In0.53Ga0.47As Esaki tunnel diode on Tunnel FET logic applications

Inter-band tunnel field effect transistors (TFETs) have recently gained a lot of interest because of their ability to eliminate the 60mV/dec sub-threshold slope (STS) limitation in MOSFET. This can result in higher ION-IOFF ratio over a reduced gate voltage range, thus predicting TFETs superior for low supply voltage (VDD ≤ 0.5V) operation. Unlike Si and Ge, III-V semiconductors like In0.53Ga0.47As have smaller tunneling barrier and tunnelling mass, thus making them a design choice to eliminate drive current (ION) limitations in TFETs [1–2]. In this work, (i) we present the experimental demonstration of record peak current density (JPEAK) In0.53Ga0.47As Esaki tunnel diode, formed using MBE grown in-situ doped epitaxial layers [4]. (ii) Using a non-local tunneling model in Sentaurus device simulator [3], the measured current-voltage characteristics (J-V) is modeled and the model parameters are calibrated. (iii) Novel In0.53Ga0.47As ultra thin body (7nm)-double gate-TFET (UTB-DG-TFET) design to boost I{ON} is discussed using the calibrated non-local tunneling model. (iv) Pulse transient response of the novel In0.53Ga0.47As TFET inverter is presented and compared with Si based MOSFET inverters at a supply voltage of 0.5V.