{"title":"半导体磁盘用SONOS非易失性存储单元","authors":"M. French, H. Sathianathan, M. White","doi":"10.1109/NVMT.1993.696955","DOIUrl":null,"url":null,"abstract":"AbstracG A SONOS EEPROM array with a true 5 volt programming voltage is proposed. An analytical expression for the change in threshold voltage as a function of time is derived as a guideline for scaling the SONOS nonvolatile memory element. An improved nonvolatile memory transistor is obtained by decreasing the tunnel oxide thickness for 20A to 18A and increasing the nitride trap density. With further reduction of the tunnel oxide thickness from 18A to 1IA , the crossover time (intersection of the erase/write curves) is improved from 60 ms to 3 ms.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A SONOS Nonvolatile Memory Cell For Semiconductor Disk Application\",\"authors\":\"M. French, H. Sathianathan, M. White\",\"doi\":\"10.1109/NVMT.1993.696955\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"AbstracG A SONOS EEPROM array with a true 5 volt programming voltage is proposed. An analytical expression for the change in threshold voltage as a function of time is derived as a guideline for scaling the SONOS nonvolatile memory element. An improved nonvolatile memory transistor is obtained by decreasing the tunnel oxide thickness for 20A to 18A and increasing the nitride trap density. With further reduction of the tunnel oxide thickness from 18A to 1IA , the crossover time (intersection of the erase/write curves) is improved from 60 ms to 3 ms.\",\"PeriodicalId\":254731,\"journal\":{\"name\":\"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NVMT.1993.696955\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMT.1993.696955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A SONOS Nonvolatile Memory Cell For Semiconductor Disk Application
AbstracG A SONOS EEPROM array with a true 5 volt programming voltage is proposed. An analytical expression for the change in threshold voltage as a function of time is derived as a guideline for scaling the SONOS nonvolatile memory element. An improved nonvolatile memory transistor is obtained by decreasing the tunnel oxide thickness for 20A to 18A and increasing the nitride trap density. With further reduction of the tunnel oxide thickness from 18A to 1IA , the crossover time (intersection of the erase/write curves) is improved from 60 ms to 3 ms.
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