一种100k栅极亚微米BiCMOS栅极阵列

J. Gallia, A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, V. Nguyen, K. Ruparel, K. Moore, C. Lemonds, B. Chae, P. Eyres, T. Yoshino, J. Pozadzides, R. Rine, Ashwin H. Shah
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引用次数: 19

摘要

开发了一种0.8 μm工艺的BiCMOS栅极阵列,在0.4 pF负载下栅极延迟为360 ps。设计了一个紧凑的基电池(750 μm2/栅极),具有全双极驱动能力。160 k门阵列建立在1.14平方厘米的芯片上,具有ECL(发射器耦合逻辑)I/O能力。放置和布线在三层金属提供阵列利用率高达92%。介绍了芯片结构和具有JTAG和两相扫描等可测试特性的双级联码数字滤波器(74k门)的实现
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 100 K gate sub-micron BiCMOS gate array
A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan
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