J. Gallia, A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, V. Nguyen, K. Ruparel, K. Moore, C. Lemonds, B. Chae, P. Eyres, T. Yoshino, J. Pozadzides, R. Rine, Ashwin H. Shah
{"title":"一种100k栅极亚微米BiCMOS栅极阵列","authors":"J. Gallia, A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, V. Nguyen, K. Ruparel, K. Moore, C. Lemonds, B. Chae, P. Eyres, T. Yoshino, J. Pozadzides, R. Rine, Ashwin H. Shah","doi":"10.1109/CICC.1989.56717","DOIUrl":null,"url":null,"abstract":"A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"23 9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A 100 K gate sub-micron BiCMOS gate array\",\"authors\":\"J. Gallia, A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, V. Nguyen, K. Ruparel, K. Moore, C. Lemonds, B. Chae, P. Eyres, T. Yoshino, J. Pozadzides, R. Rine, Ashwin H. Shah\",\"doi\":\"10.1109/CICC.1989.56717\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"23 9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56717\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56717","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan