一种超导三元收缩阵列处理机

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic Pub Date : 1992-05-27 DOI:10.1109/ISMVL.1992.186772

M. Morisue, Fu-Qiang Li

{"title":"一种超导三元收缩阵列处理机","authors":"M. Morisue, Fu-Qiang Li","doi":"10.1109/ISMVL.1992.186772","DOIUrl":null,"url":null,"abstract":"A novel Josephson ternary systolic array processor for multiplication is proposed. The processor consists of two kinds of cells, one of which performs a partial multiplication and the other two functions of multiplication and addition simultaneously. The advantages of the processor are its very simple construction with a small number of SQUID gates and its very-high-speed operation and ultralow power dissipation. Information flows between cells in a pipeline fashion so that high performance can be achieved. The principle of the processor is described in detail, and simulation results for the multiplication of 2 trit*2 trit are presented. The results show that the pipeline operation can be executed in a cycle time of 450 ps.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A superconducting ternary systolic array processor\",\"authors\":\"M. Morisue, Fu-Qiang Li\",\"doi\":\"10.1109/ISMVL.1992.186772\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel Josephson ternary systolic array processor for multiplication is proposed. The processor consists of two kinds of cells, one of which performs a partial multiplication and the other two functions of multiplication and addition simultaneously. The advantages of the processor are its very simple construction with a small number of SQUID gates and its very-high-speed operation and ultralow power dissipation. Information flows between cells in a pipeline fashion so that high performance can be achieved. The principle of the processor is described in detail, and simulation results for the multiplication of 2 trit*2 trit are presented. The results show that the pipeline operation can be executed in a cycle time of 450 ps.<<ETX>>\",\"PeriodicalId\":127091,\"journal\":{\"name\":\"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1992.186772\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1992.186772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

提出了一种新型的约瑟夫逊三元收缩阵列乘法处理器。该处理器由两种单元组成，一种单元执行部分乘法，另一种单元同时执行乘法和加法两种功能。该处理器的优点是结构简单，只使用少量的SQUID门，运行速度极快，功耗极低。信息以管道的方式在单元之间流动，从而实现高性能。详细介绍了该处理器的工作原理，并给出了2倍频乘2倍频的仿真结果。结果表明，流水线操作可在450ps的周期内完成。

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A superconducting ternary systolic array processor

A novel Josephson ternary systolic array processor for multiplication is proposed. The processor consists of two kinds of cells, one of which performs a partial multiplication and the other two functions of multiplication and addition simultaneously. The advantages of the processor are its very simple construction with a small number of SQUID gates and its very-high-speed operation and ultralow power dissipation. Information flows between cells in a pipeline fashion so that high performance can be achieved. The principle of the processor is described in detail, and simulation results for the multiplication of 2 trit*2 trit are presented. The results show that the pipeline operation can be executed in a cycle time of 450 ps.<>

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[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

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