45-32 nm工艺节点的低k/Cu混合双damascene工艺，自组装多孔硅超低k薄膜

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. Pub Date : 2005-06-06 DOI:10.1109/IITC.2005.1499919

S. Chikaki, A. Shimoyama, R. Yagi, T. Yoshino, T. Ono, A. Ishikawa, N. Fujii, N. Hata, T. Nakayama, K. Kohmura, H. Tanaka, T. Goto, J. Kawahara, Y. Sonoda, H. Matsuo, Y. Seino, S. Takada, N. Kunimi, Y. Uchida, S. Hishiya, Y. Shishida, K. Kinoshita, T. Kikkawa

{"title":"45-32 nm工艺节点的低k/Cu混合双damascene工艺，自组装多孔硅超低k薄膜","authors":"S. Chikaki, A. Shimoyama, R. Yagi, T. Yoshino, T. Ono, A. Ishikawa, N. Fujii, N. Hata, T. Nakayama, K. Kohmura, H. Tanaka, T. Goto, J. Kawahara, Y. Sonoda, H. Matsuo, Y. Seino, S. Takada, N. Kunimi, Y. Uchida, S. Hishiya, Y. Shishida, K. Kinoshita, T. Kikkawa","doi":"10.1109/IITC.2005.1499919","DOIUrl":null,"url":null,"abstract":"Self-assembled porous-silica ultra low-k films (k=2.1) were integrated for 45-32 nm technology node low-k/Cu dual damascene interconnects. Porosity and pore size distributions of the low-k film were controlled by controlling the concentration of the surfactant so that a tight distribution of dielectric constant was achieved. Self-assembled porous silica low-k/Cu damascene interconnects were successfully formed by developing dry etching, low pressure CMP, post CMP cleaning, Cu electroplating solution as well as a TMCTS process recovery treatment. The feasibility of low-k/Cu damascene was confirmed. Electrical characteristics showed a potential capability of the self-assembled porous-silica low-k film for the 45-32 nm technology node.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Hybrid low-k/Cu dual damascene process for 45-32 nm technology node using self-assembled porous-silica ultra low-k films\",\"authors\":\"S. Chikaki, A. Shimoyama, R. Yagi, T. Yoshino, T. Ono, A. Ishikawa, N. Fujii, N. Hata, T. Nakayama, K. Kohmura, H. Tanaka, T. Goto, J. Kawahara, Y. Sonoda, H. Matsuo, Y. Seino, S. Takada, N. Kunimi, Y. Uchida, S. Hishiya, Y. Shishida, K. Kinoshita, T. Kikkawa\",\"doi\":\"10.1109/IITC.2005.1499919\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Self-assembled porous-silica ultra low-k films (k=2.1) were integrated for 45-32 nm technology node low-k/Cu dual damascene interconnects. Porosity and pore size distributions of the low-k film were controlled by controlling the concentration of the surfactant so that a tight distribution of dielectric constant was achieved. Self-assembled porous silica low-k/Cu damascene interconnects were successfully formed by developing dry etching, low pressure CMP, post CMP cleaning, Cu electroplating solution as well as a TMCTS process recovery treatment. The feasibility of low-k/Cu damascene was confirmed. Electrical characteristics showed a potential capability of the self-assembled porous-silica low-k film for the 45-32 nm technology node.\",\"PeriodicalId\":156268,\"journal\":{\"name\":\"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.\",\"volume\":\"95 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2005.1499919\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2005.1499919","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

自组装多孔硅超低k薄膜(k=2.1)集成在45-32 nm技术节点低k/Cu双damascene互连。通过控制表面活性剂的浓度来控制低k膜的孔隙率和孔径分布，从而使膜的介电常数分布较紧。通过干刻蚀、低压CMP、CMP后清洗、Cu电镀溶液以及TMCTS工艺回收处理，成功制备了自组装多孔硅低k/Cu damascene互连。验证了低k/Cu改性的可行性。电学特性表明，自组装多孔二氧化硅低k膜在45-32 nm技术节点上具有潜在的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Hybrid low-k/Cu dual damascene process for 45-32 nm technology node using self-assembled porous-silica ultra low-k films

Self-assembled porous-silica ultra low-k films (k=2.1) were integrated for 45-32 nm technology node low-k/Cu dual damascene interconnects. Porosity and pore size distributions of the low-k film were controlled by controlling the concentration of the surfactant so that a tight distribution of dielectric constant was achieved. Self-assembled porous silica low-k/Cu damascene interconnects were successfully formed by developing dry etching, low pressure CMP, post CMP cleaning, Cu electroplating solution as well as a TMCTS process recovery treatment. The feasibility of low-k/Cu damascene was confirmed. Electrical characteristics showed a potential capability of the self-assembled porous-silica low-k film for the 45-32 nm technology node.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

自引率

0.00%

发文量