Look-ahead memory consistency model

We propose a hardware-centric look-ahead memory consistency model that makes the data consistent according to the special ordering requirement of memory accesses for critical sections. The novel model imposes fewer restrictions on event ordering than previously proposed models thus offering the potential of higher performance. The architecture has the following features: blocking and waking up processes by hardware; allowing instructions to be executed out-of-order; until having acquired the lock can the processor allow the requests for accessing the protected data to be evicted to the memory subsystem. The advantages of the look-ahead model include: more program segments are allowed parallel execution; locks can be released earlier, resulting in reduced waiting times for acquiring locks; and less network traffic because more write requests are merged by using two write caches.