低功耗CMOS心电放大器的设计与分析

2016 International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES) Pub Date : 2016-10-06 DOI:10.1109/ICETEESES.2016.7581404

Kamna Verma, S. Shukla, S. Jaiswal, Kumkum Verma

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引用次数: 2

摘要

本文研究了在CMOS和Vdd的不同W/L下，心电图放大器的CMRR的设计和分析。心电测量装置由测量来自人体的心电信号的电极、放大心电信号的模拟前端(AFE)放大器、将模拟心电信号数字化的模数转换器(ADC)和定期监测患者心脏的显示装置组成。随着vdd的增大，心电共模抑制比增大。不同Vdd下NMOS W/L=(37/27)时的CMRR随Vdd的增加而增加。所有仿真均在180nm CMOS技术上进行，电源电压为1.8V。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and analysis of low power CMOS ECG amplifier

This paper deals with the design and analysis of CMRR of Electrocardiogram (ECG) amplifier at different W/L of CMOS and Vdd. ECG measurement setup consists of electrodes to measure the ECG signal from the human body, an analog front end (AFE) amplifier that amplifies the ECG signal, analog to digital converter (ADC) for digitizing the analog ECG signal, and a display device to monitor the patient's heart regularly. The common mode rejection ration of ECG is increase with increasing vdd. CMRR of ECG at W/L= (37/27) of NMOS at different Vdd is increase with increase vdd. All the simulations are performed on 180nm CMOS technology with the supply voltage of 1.8V.

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2016 International Conference on Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES)

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