{"title":"用于高速片间通信的低功率电流模式多值逻辑互连","authors":"J.Q. Zhang, S. Long, F.H. Ho, J. K. Madsen","doi":"10.1109/GAAS.1995.529022","DOIUrl":null,"url":null,"abstract":"A new GaAs current mode (CM) chip-to-chip interconnection circuit is presented that provides high signal transfer speed with a 50 /spl Omega/ active termination and reduced input voltage swing. The power dissipation is shown to be 1/8 of an ECL I/O. The ternary logic version of it can reduce wiring by half and eliminate clock skew problems while still keeping the low power dissipation.","PeriodicalId":422183,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","volume":"119 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Low power current mode multi-valued logic interconnect for high speed interchip communications\",\"authors\":\"J.Q. Zhang, S. Long, F.H. Ho, J. K. Madsen\",\"doi\":\"10.1109/GAAS.1995.529022\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new GaAs current mode (CM) chip-to-chip interconnection circuit is presented that provides high signal transfer speed with a 50 /spl Omega/ active termination and reduced input voltage swing. The power dissipation is shown to be 1/8 of an ECL I/O. The ternary logic version of it can reduce wiring by half and eliminate clock skew problems while still keeping the low power dissipation.\",\"PeriodicalId\":422183,\"journal\":{\"name\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"volume\":\"119 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1995.529022\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1995.529022","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power current mode multi-valued logic interconnect for high speed interchip communications
A new GaAs current mode (CM) chip-to-chip interconnection circuit is presented that provides high signal transfer speed with a 50 /spl Omega/ active termination and reduced input voltage swing. The power dissipation is shown to be 1/8 of an ECL I/O. The ternary logic version of it can reduce wiring by half and eliminate clock skew problems while still keeping the low power dissipation.