基于IBIS的改进IO缓冲区行为建模方法的系统级验证

A. Varma, M. Steer, P. Franzon
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引用次数: 0

摘要

提出了一种新的基于IBIS(输入/输出缓冲信息规范)模型的宏观建模方法的系统级仿真和验证。讨论了[1]中讨论的黑盒技术的增强。所提出的宏模型是基于电路的,可以由模型制作者或用户定制。新的宏模型产生的模型可以准确地模拟同步开关噪声(SSN)。为了演示该解决方案,采用实际封装模型模拟了CMOS电压模驱动电路和MICRON DDR2驱动电路,并与使用IBIS模型创建的等效电路进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
System level Validation of Improved IO Buffer Behavioral Modeling Methodology Based on IBIS
System level simulation and validation of a new macromodeling methodology based on IBIS (Input/Output Buffer Information Specification) models is presented. Enhancements of the black-box techniques discussed in [1] are discussed. The proposed macromodel is circuit based and can be customized by model makers or users. The new macromodel produces models that can be simulated accurately for Simultaneous Switching Noise (SSN). To demonstrate the solution, a CMOS voltage-mode driver circuit and a MICRON DDR2 driver are simulated using real life package models and compared with equivalent circuits created with IBIS models of the same drivers.
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